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| NTMD4840N Power MOSFET Features 30 V, 7.5 A, Dual N-Channel, SOIC-8 * * * * * Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Dual SOIC-8 Surface Mount Package Saves Board Space This is a Pb-Free Device http://onsemi.com V(BR)DSS 30 V RDS(on) Max 24 mW @ 10 V 36 mW @ 4.5 V ID Max 7.5 A Applications * Disk Drives * DC-DC Converters * Printers MAXIMUM RATINGS (TJ = 25C unless otherwise stated) Rating Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current RqJA (Note 1) Power Dissipation RqJA (Note 1) Continuous Drain Current RqJA (Note 2) Power Dissipation RqJA (Note 2) Continuous Drain Current RqJA t < 10 s (Note 1) Power Dissipation RqJA t < 10 s (Note 1) Pulsed Drain Current Steady State TA = 25C TA = 70C TA = 25C TA = 25C TA = 70C TA = 25C TA = 25C TA = 70C TA = 25C TA = 25C, tp = 10 ms PD IDM TJ, TSTG IS EAS PD ID PD ID Symbol VDSS VGS ID Value 30 20 5.5 4.4 1.14 4.5 3.5 0.68 7.5 6.0 1.95 30 -55 to +150 2.0 28 W A C A mJ 4840N A Y WW G W A 8 1 W Unit V V A G N-Channel D S A MARKING DIAGRAM & PIN ASSIGNMENT D1 D1 D2 D2 8 SOIC-8 CASE 751 STYLE 11 4840N AYWW G 1 S1 G1 S2 G2 Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain-to-Source Avalanche Energy TJ = 25C, VDD = 30 V, VGS = 10 V, IL = 7.5 Apk, L = 1.0 mH, RG = 25 W Lead Temperature for Soldering Purposes (1/8 from case for 10 s) = Device Code = Assembly Location = Year = Work Week = Pb-Free Package TL 260 C ORDERING INFORMATION Device Package SOIC-8 (Pb-Free) Shipping 2500/Tape & Reel THERMAL RESISTANCE RATINGS Rating Junction-to-Ambient - Steady State (Note 1) Junction-to-Ambient - t10 s (Note 1) Junction-to-FOOT (Drain) Junction-to-Ambient - Steady State (Note 2) Symbol RqJA RqJA RqJF RqJA Max 110 64 40 183.5 C/W Unit NTMD4840NR2G Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface-mounted on FR4 board using 1 inch sq pad size, 1 oz Cu. 2. Surface-mounted on FR4 board using the minimum recommended pad size. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2009 September, 2009 - Rev. 1 1 Publication Order Number: NTMD4840N/D NTMD4840N ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)jk Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Drain-to-Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain-to-Source On Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Total Gate Charge SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time DRAIN-TO-SOURCE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time PACKAGE PARASITIC VALUES Source Inductance Drain Inductance Gate Inductance Gate Resistance LS LD LG RG TA = 25C 0.66 0.20 1.50 2.0 3.0 nH nH nH W VSD tRR Ta Tb QRR VGS = 0 V, dIS/dt = 100 A/ms, IS = 2.0 A VGS = 0 V ID = 2.0 A TJ = 25C TJ = 125C 0.76 0.58 12.5 7.3 5.2 6.0 nC ns 1.0 V td(ON) tr td(OFF) tf VGS = 10 V, VDD = 15 V, ID = 1.0 A, RG = 3.0 W 7.6 5.0 17 3.0 ns VGS(TH) VGS(TH)/TJ RDS(on) gFS CISS COSS CRSS QG(TOT) QG(TH) QGS QGD QG(TOT) VGS = 10 V, VDS = 15 V, ID = 6.9 A VGS = 4.5 V, VDS = 15 V, ID = 6.9 A VGS = 0 V, f = 1.0 MHz, VDS = 15 V VGS = 10 V VGS = 4.5 V CHARGES, CAPACITANCES AND GATE RESISTANCE 520 140 70 4.8 1.1 2.1 1.9 9.5 nC nC pF ID = 6.9 A ID = 5.0 A VGS = VDS, ID = 250 mA 1.5 6.0 16 26 15 24 36 3.0 V mV/C mW S V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS = 0 V, VDS = 24 V TJ = 25C TJ = 100C VGS = 0 V, ID = 250 mA 30 18 1.0 10 100 V mV/C mA nA Symbol Test Condition Min Typ Max Unit VDS = 0 V, VGS = 20 V VDS = 1.5 V, ID = 6.9 A 3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTMD4840N TYPICAL PERFORMANCE CURVES 12 ID, DRAIN CURRENT (AMPS) 10 8 6 3.2 V 4 2 0 3.0 V 2.8 V 2.6 V 0 1.0 2.0 3.0 4.0 5.0 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10V 4.5 V 4.2 V 4V 3.8 V 32 TJ = 25C ID, DRAIN CURRENT (AMPS) 3.4 V 28 24 20 16 12 8 4 0 1.5 2 TJ = 125C TJ = 25C 2.5 3 VDS 10 V TJ = -55C 3.5 4 4.5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.060 0.055 0.050 0.045 0.040 0.035 0.030 0.025 0.020 0.015 3 4 5 6 7 8 9 TJ = 25C ID = 6.9 A RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.030 0.028 0.026 0.024 0.022 0.020 0.018 0.016 0.014 2 3.5 Figure 2. Transfer Characteristics TJ = 25C VGS = 4.5 V VGS = 10 V 10 5 6.5 8 9.5 11 12.5 14 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-to-Source Voltage 1.65 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.55 1.45 1.35 1.25 1.15 1.05 0.95 0.85 0.75 0.65 -50 -25 0 25 50 75 100 125 150 100 ID = 7.5 A VGS = 10 V IDSS, LEAKAGE (nA) 10000 100000 Figure 4. On-Resistance vs. Drain Current and Gate Voltage VGS = 0 V TJ = 150C 1000 TJ = 125C 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 3 NTMD4840N TYPICAL PERFORMANCE CURVES TJ = 25C Ciss VGS = 0 V VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 700 600 C, CAPACITANCE (pF) 500 400 300 200 100 0 Crss 0 5 10 15 20 25 DRAIN-TO-SOURCE VOLTAGE (VOLTS) 30 Coss 10 9 8 7 6 5 4 3 2 1 0 0 1 2 VGS = 10 V ID = 6.9 A TJ = 25C 8 3 5 6 7 4 QG, TOTAL GATE CHARGE (nC) 9 10 QGS QGD VDS VGS QT Figure 7. Capacitance Variation Figure 8. Gate-To-Source and Drain-To-Source Voltage vs. Total Charge 100 td(off) tf t, TIME (ns) 10 IS, SOURCE CURRENT (AMPS) VDD = 15 V ID = 1 A VGS = 10 V 2.5 2 VGS = 0 V TJ = 25C 1.5 1 td(on) tr 0.5 0 0.4 1 1 10 RG, GATE RESISTANCE (OHMS) 100 0.5 0.6 0.7 0.8 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 100 ID, DRAIN CURRENT (AMPS) 10 ms 10 100 ms 1 ms 1 VGS = 20 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 10 ms 30 25 20 15 10 5 Figure 10. Diode Forward Voltage vs. Current ID = 7.5 A 0.1 dc 0.01 0.01 100 0 25 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150 Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 NTMD4840N PACKAGE DIMENSIONS SOIC-8 NB CASE 751-07 ISSUE AJ A 8 5 -X- B 1 S 4 0.25 (0.010) M Y M -Y- G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 C -Z- H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 5 NTMD4840N/D |
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